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| ? 2007 microchip technology inc. ds22003d-page 1 mcp3421 features ? 18-bit ? adc in a sot-23-6 package ? differential input operation ? self calibration of internal offset and gain per each conversion ? on-board voltage reference: - accuracy: 2.048v 0.05% - drift: 15 ppm/c ? on-board programmable gain amplifier (pga): - gains of 1,2, 4 or 8 ? on-board oscillator ? inl: 10 ppm of fsr (fsr = 4.096v/pga) ? programmable data rate options: - 3.75 sps (18 bits) - 15 sps (16 bits) - 60 sps (14 bits) - 240 sps (12 bits) ? one-shot or continuous conversion options ? low current consumption: - 145 a typical (v dd = 3v, continuous conversion) - 39 a typical (v dd = 3v, one-shot conv ersion with 1 sps) ? supports i 2 c serial interface: - standard, fast and high speed modes ? single supply operation: 2.7v to 5.5v ? extended temperature range: -40c to 125c typical applications ? portable instrumentation ? weigh scales and fuel gauges ? temperature sensing with rtd, thermistor, and thermocouple ? bridge sensing for pressure, strain, and force. package types description the mcp3421 is a single channel low-noise, high accuracy ? a/d converter with differential inputs and up to 18 bits of resolution in a small sot-23-6 package. the on-board precision 2. 048v reference voltage enables an input range of 2.048v differentially ( voltage = 4.096v). the device uses a two-wire i 2 c compatible serial interface and operates from a single 2.7v to 5.5v power supply. the mcp3421 device performs conversion at rates of 3.75, 15, 60, or 240 samples per second (sps) depending on the user cont rollable configuration bit settings using the two-wire i 2 c serial interface. this device has an on-board programmable gain amplifier (pga). the user can select the pga gain of x1, x2, x4, or x8 before the analog-to-digital conversion takes place. this allows the mcp3421 device to convert a smaller input signal with high resolution. the device has two conversion modes: (a) continuous mode and (b) one-shot mode. in one-shot mode, the device enters a low current standby mode automatically after one conversion. this reduces current consumption greatly during idle periods. the mcp3421 device can be used for various high accuracy analog-to-digital data conversion applications where design simplicity, low power, and small footprint are major considerations. block diagram 1 2 3 4 5 6 v in + v ss scl v in - v dd sda top view sot-23-6 v ss v dd v in + v in - scl sda voltage reference clock (2.048v) i 2 c interface gain = 1, 2, 4, or 8 v ref ? adc converter pga oscillator 1 8 - b i t a n a l o g - t o - d i g i t a l c o n v e r t e r with i 2 c interface and on-board reference
mcp3421 ds22003d-page 2 ? 2007 microchip technology inc. 1.0 electrical characteristics 1.1 absolute maximum ratings? v dd ...................................................................................7.0v all inputs and outputs w.r.t v ss ............... ?0.3v to v dd +0.3v differential input voltage ...................................... |v dd - v ss | output short circuit current .................................continuous current at input pins ....................................................2 ma current at output and supply pins ............................10 ma storage temperature.....................................-65c to +150c ambient temp. with power applied ...............-55c to +125c esd protection on all pins ................ 6kv hbm, 400v mm maximum junction temperature (t j ) . .........................+150c ?notice: stresses above those listed under ?maximum rat- ings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability . 1.2 electrical specifications table 1-1: electrical characteristics electrical specifications: unless otherwise specified, all parameters apply for t a = -40c to +85c, v dd = +5.0v, v ss = 0v, v in + = v in - = v ref /2. all ppm units use 2*v ref as full-scale range. parameters sym min typ max units conditions analog inputs differential input range ? 2.048/pga ? v v in = v in + - v in - common-mode voltage range (absolute) (note 1) v ss -0.3 ? v dd +0.3 v differential input impedance (note 2) z ind (f) ? 2.25/pga ? m during normal mode operation common mode input impedance z inc (f) ? 25 ? m pga = 1, 2, 4, 8 system performance resolution and no missing codes (note 8) 12 ? ? bits dr = 240 sps 14 ? ? bits dr = 60 sps 16 ? ? bits dr = 15 sps 18 ? ? bits dr = 3.75 sps data rate (note 3) dr 176 240 328 sps s1,s0 = ?00?, (12 bits mode) 44 60 82 sps s1,s0 = ?01?, (14 bits mode) 11 15 20.5 sps s1,s0 = ?10?, (16 bits mode) 2.75 3.75 5.1 sps s1,s0 = ?11?, (18 bits mode) output noise ? 1.5 ? v rms t a = 25c, dr = 3.75 sps, pga = 1, v in = 0 integral nonlinearity (note 4) inl ? 10 35 ppm of fsr dr = 3.75 sps (note 6) internal reference voltage v ref ? 2.048 ? v gain error (note 5) ? 0.05 0.35 % pga = 1, dr = 3.75 sps note 1: any input voltage below or greater than this voltage causes leakage current through the esd diodes at the input pins. this parameter is ensured by characterization and not 100% tested. 2: this input impedance is due to 3.2 pf internal input sampling capacitor. 3: the total conversion speed includes aut o-calibration of offset and gain. 4: inl is the difference between the endpoints line and the measured code at the center of the quantization band. 5: includes all errors from on-board pga and v ref . 6: full scale range (fsr) = 2 x 2.048/pga = 4.096/pga. 7: this parameter is ensured by characterization and not 100% tested. 8: this parameter is ensured by design and not 100% tested. ? 2007 microchip technology inc. ds22003d-page 3 mcp3421 pga gain error match (note 5) ? 0.1 ? % between any 2 pga gains gain error drift ( note 5 ) ? 15 ? ppm/c pga=1, dr=3.75 sps offset error v os ? 15 40 v tested at pga = 1 v dd = 5.0v and dr = 3.75 sps offset drift vs. temperature ? 50 ? nv/c v dd = 5.0v common-mode rejection ? 105 ? db at dc and pga =1, ? 110 ? db at dc and pga =8, t a = +25c gain vs. v dd ? 5 ? ppm/v t a = +25c, v dd = 2.7v to 5.5v, pga = 1 power supply rejection at dc ? 100 ? db t a = +25c, v dd = 2.7v to 5.5v, pga = 1 power requirements voltage range v dd 2.7 ? 5.5 v supply current during conversion i dda ? 155 190 a v dd = 5.0v ? 145 ? a v dd = 3.0v supply current during standby mode i dds ?0.1 0.5a i 2 c digital inputs and digital outputs high level input voltage v ih 0.7 v dd ?v dd v low level input voltage v il ? ? 0.3v dd v low level output voltage v ol ?? 0.4 vi ol = 3 ma, v dd = +5.0v hysteresis of schmitt trigger for inputs (note 7) v hyst 0.05v dd ??vf scl = 100 khz supply current when i 2 c bus line is active i ddb ?? 10a input leakage current i ilh ?? 1 av ih = 5.5v i ill -1 ? ? a v il = gnd pin capacitance and i 2 c bus capacitance pin capacitance c pin ? ? 10 pf i 2 c bus capacitance c b ? ? 400 pf thermal characteristics specified temperature range t a -40 ? +85 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c table 1-1: electrical characteristics (continued) electrical specifications: unless otherwise specified, all parameters apply for t a = -40c to +85c, v dd = +5.0v, v ss = 0v, v in + = v in - = v ref /2. all ppm units use 2*v ref as full-scale range. parameters sym min typ max units conditions note 1: any input voltage below or greater than this voltage causes leakage current through the esd diodes at the input pins. this parameter is ensured by characterization and not 100% tested. 2: this input impedance is due to 3.2 pf internal input sampling capacitor. 3: the total conversion speed includes aut o-calibration of offset and gain. 4: inl is the difference between the endpoints line and the measured code at the center of the quantization band. 5: includes all errors from on-board pga and v ref . 6: full scale range (fsr) = 2 x 2.048/pga = 4.096/pga. 7: this parameter is ensured by characterization and not 100% tested. 8: this parameter is ensured by design and not 100% tested. mcp3421 ds22003d-page 4 ? 2007 microchip technology inc. 2.0 typical performance curves note: unless otherwise indicated, t a = -40c to +85c, v dd = +5.0v, v ss = 0v, v in + = v in - = v ref /2. figure 2-1: inl vs. supply voltage (v dd ). figure 2-2: inl vs. temperature. figure 2-3: offset error vs. temperature. figure 2-4: noise vs. input voltage. figure 2-5: total error vs. input voltage. figure 2-6: gain error vs. temperature. note: the graphs and tables provided following this note ar e a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. .000 .001 .002 .003 .004 .005 2.5 3 3.5 4 4.5 5 5.5 v dd (v) pga = 1 pga = 2 pga = 8 pga = 4 integral nonlinearity (% of fsr) 0 0.001 0.002 0.003 -60 -40 -20 0 20 40 60 80 100 120 140 temperature ( o c) integral nonlinearity (% of fsr) v dd = 5 v v dd = 2.7v pga = 1 -20 -15 -10 -5 0 5 10 15 20 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) offset error (v) v dd = 5v pga = 1 pga = 2 pga = 8 pga = 4 0.0 2.5 5.0 7.5 10.0 -100 -75 -50 -25 0 25 50 75 100 input voltage (% of full-scale) noise (v, rms) pga = 1 pga = 2 pga = 8 pga = 4 t a = +25c v dd = 5v -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 -100 -75 -50 -25 0 25 50 75 100 input voltage (% of full-scale) total error (mv) pga = 1 pga = 2 pga = 8 pga = 4 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) gain error (% of fsr) v dd = 5.0v pga = 1 pga = 2 pga = 8 pga = 4 ? 2007 microchip technology inc. ds22003d-page 5 mcp3421 note: unless otherwise indicated, t a = -40c to +85c, v dd = +5.0v, v ss = 0v, v in + = v in - = v ref /2. figure 2-7: i dda vs. temperature. figure 2-8: i dds vs. temperature. figure 2-9: i ddb vs. temperature. figure 2-10: osc drift vs. temperature. figure 2-11: frequency response. 100 120 140 160 180 200 220 -60 -40 -20 0 20 40 60 80 100 120 140 temperature ( o c) i dda (a) v dd = 5v v dd = 2.7v 0 100 200 300 400 500 600 -60 -40 -20 0 20 40 60 80 100 120 140 temperature ( o c) i dds (na) v dd = 2.7v v dd = 5v 0 1 2 3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100 120 140 temperature ( o c) i ddb ( p a) v dd = 5v v dd = 4.5v v dd = 3.3v v dd = 2.7v -1 0 1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) oscillator drift (%) v dd = 5.0v v dd = 2.7v data rate = 3.75 sps -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.1 1 10 100 1000 10000 input signal frequency (hz) magnitude (db) 0.1 1 10 100 1k 10k mcp3421 ds22003d-page 6 ? 2007 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 analog inputs (v in +, v in -) v in + and v in - are differential signal input pins. the mcp3421 device accepts a fully differential analog input signal which is connected on the v in + and v in - input pins. the differential voltage that is converted is defined by v in = (v in + - v in -) where v in + is the voltage applied at the v in + pin and v in - is the voltage applied at the v in - pin. the input signal level is amplified by the programmable gain ampl ifier (pga) before the conversion. the differential input voltage should not exceed an absolute of (v ref /pga) for accurate measurement, where v ref is the internal reference voltage (2.048v) and pga is the pga gain setting. the converter output code will saturate if the input range exceeds (v ref /pga). the absolute voltage range on each of the differential input pins is from v ss -0.3v to v dd +0.3v. any voltage above or below this range will cause leakage currents through the electrostatic discharge (esd) diodes at the input pins. this esd current can cause unexpected performance of the device. the common mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in section 1.0 ?electrical characteristics? and section 4.0 ?description of device operation? . 3.2 supply voltage (v dd , v ss ) v dd is the power supply pin for the device. this pin requires an appropriate bypass capacitor of about 0.1 f (ceramic) to ground. an additional 10 f capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in some application boards. the supply voltage (v dd ) must be maintained in the 2.7v to 5.5v range for spec- ified operation. v ss is the ground pin and the current return path of the device. the user must connect the v ss pin to a ground plane through a low impedance connection. if an analog ground path is available in the application pcb (printed circuit board), it is highly recommended that the v ss pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.3 serial clock pin (scl) scl is the serial clock pin of the i 2 c interface. the mcp3421 acts only as a slave and the scl pin accepts only external seri al clocks. the input data from the master device is shifted into the sda pin on the rising edges of the scl clock and output from the mcp3421 occurs at the falling edges of the scl clock. the scl pin is an open-drain n-channel driver. therefore, it needs a pul l-up resistor from the v dd line to the scl pin. refer to section 5.3 ?i 2 c serial com- munications? for more details of i 2 c serial interface communication. 3.4 serial data pin (sda) sda is the serial data pin of the i 2 c interface. the sda pin is used for input and output data. in read mode, the conversion result is read fr om the sda pin (output). in write mode, the device config uration bits are written (input) though the sda pin. the sda pin is an open- drain n-channel driver. ther efore, it needs a pull-up resistor from the v dd line to the sda pin. except for start and stop conditions, the data on the sda pin must be stable during the high period of the clock. the high or low state of the sda pin can only change when the clock signal on the scl pin is low. refer to section 5.3 ?i 2 c serial communications? for more details of i 2 c serial interface communication. pin no sym function 1v in + non-inverting analog input pin 2v ss ground pin 3scl serial clock input pin of the i 2 c interface 4sda bidirectional serial data pin of the i 2 c interface 5v dd positive supply voltage pin 6v in - inverting analog input pin ? 2007 microchip technology inc. ds22003d-page 7 mcp3421 4.0 description of device operation 4.1 general overview the mcp3421 is a low-power, 18-bit delta-sigma a/d converter with an i 2 c serial interface. the device contains an on-board voltage reference (2.048v), programmable gain amplifier (pga), and internal oscillator. the user can select 12, 14, 16, or 18 bit conversion by setting the co nfiguration register bits. the device can be operated in continuous conversion or one-shot conversion mode. in the continuous conversion mode, the device converts the inputs continuously. while in the one-shot conversion mode, the device converts the input one time and stays in the low-power standby mode until it receives another command for a new conversion. during the standby mode, the device consumes less than 0.1 a typical. 4.2 power-on-reset (por) the device contains an internal power-on-reset (por) circuit that monito rs power supply voltage (v dd ) during operation. this circuit ensures correct device start-up at system power-up and power-down events. the por has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. a 0.1 f decoupling capacitor should be mounted as close as possible to the v dd pin for additional transient immunity. the threshold voltage is set at 2.2v with a tolerance of approximately 5%. if the supply voltage falls below this threshold, the device will be held in a reset condition. the typical hyster esis value is approximately 200 mv. the por circuit is shut-down during the low-power standby mode. once a power-up event has occurred, the device requires additional delay time (approxi- mately 300 s) before a conversion can take place. during this time, all internal analog circuitries are settled before the first conversion occurs. figure 4-1 illustrates the conditions for power-up and power-down events under typical start-up conditions. when the device powers up, it automatically resets and sets the configuration bi ts to default settings. the default configuration bit c onditions are a pga gain of 1 v/v and a conversion speed of 240 sps in continuous conversion mode. when the device receives an i 2 c general call reset command, it performs an internal reset similar to a power-on-reset event. figure 4-1: por operation. 4.3 internal voltage reference the device contains an on-board 2.048v voltage reference. this reference vo ltage is for internal use only and not directly measurable. the specifications of the reference voltage are part of the device?s gain and drift specifications. therefore, there is no separate specification for the on-board reference. 4.4 analog input channel the differential analog input channel has a switched capacitor structure. the in ternal sampling capacitor (3.2 pf) is charged and discharged to process a conversion. the charging and discharging of the input sampling capacitor creates dynamic input currents at the v in + and v in - input pins, which is inversely proportional to the internal sampling capacitor and internal frequency. the current is also a function of the differential input voltages. care must be taken in setting the common-mode voltage and input voltage ranges so that the input limits do not exceed the ranges specified in section 1.0 ?electrical characteristics? . 4.5 digital output code the digital output code produced by the mcp3421 is a function of pga gain, input signal, and internal reference voltage. in a fixed setting, the digital output code is proportional to the voltage difference between the two analog inputs. the output data format is a binary two?s complement. with this code scheme, the msb can be considered a sign indicator. when the msb is a logic ? 0 ?, it indicates a positive value. when the msb is a logic ? 1 ?, it indicates a negative value. the following is an example of the output code: (a) for a negative full-scale input voltage: 100...000 (b) for a zero differential input voltage: 000...000 (c) for a positive full-scale input voltage: 011...111. the msb is always transmitted first through the serial port. the number of data bits for each conversion is 18, 16, 14, or 12 bits depending on the conversion mode selection. v dd 2.2v 2.0v 300 s reset start-up normal operation reset time mcp3421 ds22003d-page 8 ? 2007 microchip technology inc. the output codes will not roll-over if the input voltage exceeds the maximum input range. in this case, the code will be locked at 0111...11 for all voltages greater than +(v ref - 1 lsb) and 1000...00 for voltages less than -v ref . ta b l e 4 - 2 shows an example of output codes of various input levels using 18 bit conversion mode. ta b l e 4 - 3 shows an example of minimum and maximum codes for each data rate option. the output code is given by: equation 4-1: the lsb of the code is given by: equation 4-2: table 4-1: lsb size of various bit conversion modes table 4-2: example of output code for 18 bits table 4-3: minimum and maximum codes 4.6 self-calibration the device performs a self-calibration of offset and gain for each conversion. this provides reliable conversion results from conv ersion-to-conversion over variations in temperature as well as power supply fluctuations. 4.7 input impedance the mcp3421 uses a switched-capacitor input stage using a 3.2 pf sampling capa citor. this capacitor is switched (charged and discharged) at a rate of the sampling frequency that is generated by the on-board clock. the differential mode impedance varies with the pga settings. the typical differential input impedance during a normal mode operation is given by: since the sampling capacitor is only switching to the input pins during a conver sion process, the above input impedance is only valid during conversion periods. in a low power standby mode, the above impedance is not presented at the input pins. therefore, only a leakage current due to esd diode is presented at the input pins. the conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. the source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. therefore, a large input so urce impedance connected to the input pins can increase the system performance errors such as offset, gain, and integral nonlinearity (inl) errors. ideally, the input source impedance should be zero. this can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms. bit resolutions lsb (v) 12 bits 1 mv 14 bits 250 v 16 bits 62.5 v 18 bits 15.625 v input voltage (v) digital code v ref 011111111111111111 v ref - 1 lsb 011111111111111111 2lsb 000000000000000010 1lsb 000000000000000001 0 000000000000000000 -1 lsb 111111111111111111 -2 lsb 111111111111111110 - v ref 100000000000000000 < -v ref 100000000000000000 output code max code 1 + () v in +v in - ? () 2.048v -------------------------------------- - = lsb 2 2.048v 2 n -------------------------- = where: n = number of bits number of bits data rate minimum code maximum code 12 240 sps -2048 2047 14 60 sps -8192 8191 16 15 sps -32768 32767 18 3.75 sps -131072 131071 note: maximum n-bit code = 2 n-1 - 1 minimum n-bit code = -1 x 2 n-1 z in (f) = 2.25 m /pga ? 2007 microchip technology inc. ds22003d-page 9 mcp3421 4.8 aliasing and anti-aliasing filter aliasing occurs when the input signal contains time- varying signal components with frequency greater than half the sample rate. in the aliasing conditions, the device can output unexpect ed output codes. for applications that are operating in electrical noise environments, the time-varying signal noise or high frequency interference components can be easily added to the input signals and cause aliasing. although the mcp3421 device has an internal first order sinc filter, its? filter response may not give enough attenuation to all aliasing signal components. to avoid the aliasing, an external anti-aliasing filter, which can be accomplished with a simple rc low-pass filter, is typically used at the input pins. the low-pass filter cuts off the high frequency noise components and provides a band-limited input signal to the mcp3421 input pins. mcp3421 ds22003d-page 10 ? 2007 microchip technology inc. 5.0 using the mcp3421 device 5.1 operating modes the user operates the devic e by setting up the device configuration register an d reads the conversion data using serial i 2 c interface commands. the mcp3421 operates in two modes: (a) continuous conversion mode or (b) one-shot conversion mode (single conversion). the selection is made by setting the o /c bit in the configuration register. refer to section 5.2 ?configuration register? for more information. 5.1.1 continuous conversion mode (o /c bit = 1 ) the mcp3421 device performs a continuous conversion if the o /c bit is set to logic ?high?. once the conversion is completed, the result is placed at the output data register. the device immediately begins another conversion and ov erwrites the output data register with the most recent data. the device also clears the data ready flag (rdy bit = 0 ) when the conversion is completed. the device sets the ready flag bit (rdy bit = 1 ), if the latest conversion result has been read by the master. 5.1.2 one-shot conversion mode (o /c bit = 0 ) once the one-shot conversion (single conversion) mode is selected, the device performs a conversion, updates the output data register, clears the data ready flag (rdy = 0 ), and then enters a low power standby mode. a new one-shot conv ersion is started again when the device receives a new write command with rdy = 1 . this one-shot conversion mode is recommended for low power operating applications. during the low current standby mode, the device consumes less than 1 a typical. for example, if user collects 18 bit conversion data once a second in one-shot conver- sion mode, the device draws only about one fourth of its total operating current. in this example, the device consumes approximately 39 a (= ~145 a/3.75 sps), if the device performs only one conversion per second (1 sps) in 18-bit conversion mode with 3v power supply. ? 2007 microchip technology inc. ds22003d-page 11 mcp3421 5.2 configuration register the mcp3421 has an 8-bit wide configuration register to select for: pga gain, conversion rate, and conver- sion mode. this register allows the user to change the operating condition of the device and check the status of the device operation. th e user can rewrite the configuration byte any time during the device operation. register 5-1 shows the configuration register bits. register 5-1: configuration register r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 rdy c1 c0 o /c s1 s0 g1 g0 1 * 0 * 0 * 1 * 0 * 0 * 0 * 0 * bit 7 bit 0 * default configuration after power-on reset legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rdy : ready bit this bit is the data ready flag. in read mode, this bit indicates if the output register has been updated with a new conversion. in one-shot c onversion mode, writing this bit to ? 1 ? initiates a new conversion. reading rdy bit with the read command: 1 = output register has not been updated. 0 = output register has been update d with the latest conversion data. writing rdy bit with the write command: continuous conversion mode: no effect one-shot conversion mode: 1 = initiate a new conversion. 0 = no effect. bit 6-5 c1-c0: channel selection bits these are the channel selection bits, but not used in the mcp3421 device. bit 4 o /c: conversion mode bit 1 = continuous conversion mode. once this bit is selected, the device performs data conversions continuously. 0 = one-shot conversion mode. the device performs a single conversion and enters a low power standby mode until it receives another write/read command. bit 3-2 s1-s0: sample rate selection bit 00 = 240 sps (12 bits), 01 = 60 sps (14 bits), 10 = 15 sps (16 bits), 11 = 3.75 sps (18 bits) bit 1-0 g1-g0: pga gain selector bits 00 = 1 v/v, 01 = 2 v/v, 10 = 4 v/v, 11 = 8 v/v mcp3421 ds22003d-page 12 ? 2007 microchip technology inc. in read mode, the rdy bit in the configuration byte indicates the state of the conversion: (a) rdy = 1 indicates that the data bytes that have just been read were not updated from the previous conversion. (b) rdy = 0 indicates that the data bytes that have just been read were updated. if the configuration byte is read repeatedly by clocking continuously after the first read (i.e., after the 5th byte in the 18-bit conversion mode), the state of the rdy bit indicates whether the device is ready with new conversion data. see figure 5-2 . for example, rdy = 0 means new conversion data is ready for read- ing. in this case, the user can send a stop bit to exit the current read operation and send a new read command to read out updated conversion data. see figures 5-2 and 5-3 for reading conversion data. the user can rewrite the configuration byte any time for a new setting. tables 5-1 and 5-2 show the examples of the configuration bit operation. 5.3 i 2 c serial communications the mcp3421 device communicates with master (microcontroller) th rough a serial i 2 c (inter-integrated circuit) interface and supports standard (100 kbits/ sec), fast (400 kbits/sec) and high-speed (3.4 mbits/ sec) modes. the serial i 2 c is a bidirectional 2-wire data bus communication protocol using open-drain scl and sda lines. the mcp3421 can only be addressed as a slave. once addressed, it can receive c onfiguration bits or transmit the latest conversion results. the serial clock pin (scl) is an input only and the serial data pin (sda) is bidirectional. an exampl e of a hardware connection diagram is shown in figure 6-1 . the master starts communication by sending a start bit and terminates the communication by sending a stop bit. the first byte after the start bit is always the address byte of the device, which includes the device code, the address bits, and the r/w bit. the device code for the mcp3421 device is 1101 . the address bits (a2, a1, a0) are pre-programmed at the factory. in general, the address bits are specified by the customer when they orde r the device. the three address bits are programmed to ? 000 ? at the factory, if they are not specified by the customer. figure 5-1 shows the details of the mcp3421 address byte. during a low power standby mode, sda and scl pins remain at a floating condition. more details of the i 2 c bus characteristic is described in section 5.6 ?i 2 c bus characteristics? . 5.3.1 device addressing the address byte is the first byte received following the start condition from the master device. the mcp3421 device code is 1101 . the device code is followed by three address bits (a2, a1, a0) which are programmed at the factory. the three address bits allow up to eight mcp3421 devices on the same data bus line. the (r/w ) bit determines if the master device wants to read the conversion data or write to the configuration register. if the (r/w ) bit is set (read mode), the mcp3421 outputs the conversion data in the following clocks. if the (r/w ) bit is cleared (write mode), the mcp3421 expects a configuration byte in the following clocks. when the mcp3421 receives the correct address byte, it outputs an acknowledge bit after the r/w bit. figure 5-1 shows the mcp3421 address byte. see figures 5-2 and 5-3 for the read and write operations of the device. table 5-1: configuration bits for writing r/w o /c rdy operation 0 0 0 no effect if all other bits remain the same - operation continues with the previous settings 0 0 1 initiate one-shot conversion 0 1 0 initiate continuous conversion 0 1 1 initiate continuous conversion table 5-2: configuration bits for reading r/w o /c rdy operation 1 0 0 new conversion data in one- shot conversion mode has been just read. the rdy bit remains low until set by a new write command. 1 0 1 one-shot conversion is in progress, the conversion data is not updated yet. the rdy bit stays high. 1 1 0 new conversion data in continu- ous conversion mode has been just read. the rdy bit changes to high after this read. 1 1 1 the conversion data in continu- ous conversion mode was already read. the latest conver- sion data is not ready. the rdy bit stays high until a new conversion is completed. ? 2007 microchip technology inc. ds22003d-page 13 mcp3421 figure 5-1: mcp3421 address byte. 5.3.2 reading data from the device when the master sends a read command (r/w = 1 ), the mcp3421 outputs the conversion data bytes and configuration byte. each byte consists of 8 bits with one acknowledge (ack) bit. the ack bit after the address byte is issued by the mcp3421 and the ack bits after each conversion data bytes are issued by the master. when the device is configured for 18-bit conversion mode, the device outputs three data bytes followed by a configuration byte. the first 7 data bits in the first data byte are the msb of the conversion data. the user can ignore the first 6 data bits, and take the 7th data bit (d17) as the msb of the conversion data. the lsb of the 3rd data byte is the lsb of the conversion data (d0). if the device is configured fo r 12, 14, or 16 bit-mode, the device outputs two data bytes followed by a configuration byte. in 16 bi t-conversion mode, the msb of the first data byte is the msb (d15) of the conversion data. in 14-bit conversion mode, the first two bits in the first data byte can be ignored (they are the msb of the conversion data), and the 3rd bit (d13) is the msb of the conversion data. in 12 -bit conversion mode, the first four bits can be igno red (they are the msb of the conversion data), and the 5t h bit (d11) of the byte represents the msb of the conversion data. table 5-3 shows an example of the conversion data output of each conversion mode. the configuration byte follows the output data byte. the device outputs the configuration byte as long as the scl pulses are received. the device terminates the current outputs when it receives a not-acknowl- edge (nak), a repeated start or a stop bit at any time during the output bit stream. it is not required to read the configuration byte. however, the user may read the configuration byte to check the rdy bit condition to confirm whether the just received data bytes are updated conversion data. th e user may continuously send clock (scl) to repeat edly read the configuration bytes to check the rdy bit status. figures 5-2 and 5-3 show the timing diagrams of the reading. 5.3.3 writing a configuration byte to the device when the master sends an address byte with the r/w bit low (r/w = 0 ), the mcp3421 expects one configuration byte following the address. any byte sent after this second byte will be ignored. the user can change the operating mode of the device by writing the configuration register bits. if the device receives a write command with a new configuration setting, the device immediately begins a new conversion and updates the conversion data. start bit read/write bit address byte r/w ack 1 1 0 1 x x x device code address bits (note 1) address acknowledge bit address note 1: specified by customer and programmed at the factory. if not specified by the customer, programmed to ? 000 ?. table 5-3: example of conversion data output of each conversion mode conversion mode conversion data output 18-bits mmmmmmmd16 (1st data byte) - d15 ~ d8 (2nd data byte) - d7 ~ d0 (3rd da ta byte) - configuration byte 16-bits md14~d8 (1st data byte) - d7 ~ d0 (2nd data byte) - configuration byte 14-bits mmmd12~d8 (1st data byte) - d7 ~ d0 (2nd data byte) - configuration byte 12-bits mmmmmd10d9d8 (1st data byte) - d7 ~ d0 (2nd data byte) - configuration byte note: m is msb of the data byte. mcp3421 ds22003d-page 14 ? 2007 microchip technology inc. figure 5-2: timing diagram for reading from the mcp3421 with 18-bit mode. 9 1 9 1 9 19 1 9 1 9 1 1 1 0 1 a2 a1 a0 d rdy o /c ack by mcp3421 7 r/w start bit by master repeat of d17 (msb) 2nd byte upper data byte (data on clocks 1-6th can be ignored) ack by master ack by master ack by master ack by master 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 c 1 c 0 s 1 s 0 g 1 g 0 1st byte mcp3421 address byte 3rd byte middle data byte 4th byte lower data byte 5th byte configuration byte (optional) c 1 c 0 s 1 s 0 g 1 g 0 nak by master stop bit by master (optional) nth repeated byte: configuration byte note: ? mcp3421 device code is 1101 . ? address bits a2- a0 = 000 are programmed at the factory unless customer requests specific codes. ? stop bit or nak bit can be issued any time during reading. ? data bits on clocks 1 - 6th in 2nd byte are repeated msb and can be ignored. scl sda rdy o /c ? 2007 microchip technology inc. ds22003d-page 15 mcp3421 figure 5-3: timing diagram for reading from the mcp3421 with 12-bit to 16-bit modes. 1 1 0 1 a2 a1 a0 ack by mcp3421 start bit by master 2nd byte middle data byte ack by master ack by master ack by master d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 c 1 c 0 s 1 s 0 g 1 g 0 1st byte mcp3421 address byte 3rd byte lower data byte 4th byte configuration byte (optional) c 1 c 0 s 1 s 0 g 1 g 0 nak by master stop bit by master (optional) nth repeated byte: configuration byte note: ? mcp3421 device code is 1101 . ? address bits a2- a0 = 000 are programmed at the factory unle ss customer requests specific codes. ? stop bit or nak bit can be issued any time during reading. ? in 14 - bit mode: d15 and d14 are repeated msb and can be ignored. ? in 12 - bit mode: d15 - d12 ar e repeated msb and can be ignored. 9 1 99 1 9 1 9 1 scl sda 9 1 rdy o /c r/w rdy o /c mcp3421 ds22003d-page 16 ? 2007 microchip technology inc. figure 5-4: timing diigram for writing to the mcp3421. 5.4 general call the mcp3421 acknowledges the general call address (0x00 in the first byte). th e meaning of the general call address is always specified in the second byte. refer to figure 5-5 . the mcp3421 supports the following general calls: 5.4.1 general call reset the general call reset occurs if the second byte is ? 00000110 ? (06h). at the acknowledgement of this byte, the device will abort current conversion and perform an internal reset si milar to a power-on-reset (por). 5.4.2 general call conversion the general call conversion occurs if the second byte is ? 00001000 ? (08h). all devices on the bus initiate a conversion simultaneously. for the mcp3421 device, the configuration will be set to the one-shot conver- sion mode and a single conversion will be performed. the pga and data rate settings are unchanged with this general call. figure 5-5: general call address format. for more information on the general call, or other i 2 c modes, please refer to the phillips i 2 c specification. 9 1 9 1 stop bit by 11 0 1a2a1 a0 r/w ack by mcp3421 rd y c1 c0 o /c s1 s0 g1 g0 1st byte: 2nd byte: master ack by mcp3421 mcp3421 address byte configuration byte start bit by master with write command note: ? stop bit can be issued any time during writing. ? mcp3421 device code is 1101 . ? address bits a2- a0 = 000 are programmed at factory unless customer requests different codes. scl sda note: the i 2 c specification does not allow to use ? 00000000 ? (00h) in the second byte. lsb first byte ack x 0 0 0 0 0 0 0 0 a a xxxxxxx (general call address) second byte ack ? 2007 microchip technology inc. ds22003d-page 17 mcp3421 5.5 high-speed (hs) mode the i 2 c specification requires that a high-speed mode device must be ?activated? to operate in high-speed mode. this is done by sending a special address byte of 00001xxx following the start bit. the xxx bits are unique to the high-speed (hs) mode master. this byte is referred to as the high-speed (hs) master mode code (hsmmc). the mcp3421 device does not acknowledge this byte. however, upon receiving this code, the mcp3421 switches on its hs mode filters and communicates up to 3.4 mhz on sda and scl. the device will switch out of the hs mode on the next stop condition. for more information on the hs mode, or other i 2 c modes, please refer to the phillips i 2 c specification. 5.6 i 2 c bus characteristics the i 2 c specification defines the following bus protocol: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined using figure 5-6 . 5.6.1 bus not busy (a) both data and clock lines remain high. 5.6.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 5.6.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determi nes a stop condition. all operations can be ended with a stop condition. 5.6.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is init iated with a start condition and terminated with a stop condition. 5.6.5 acknowledge the master (microcontroller) and the slave (mcp3421) use an acknowledge pulse as a hand shake of communication for each byte. the ninth clock pulse of each byte is used for the acknowledgement. the acknowledgement is achieved by pulling-down the sda line ?low? during the 9th clock pulse. the clock pulse is always provided by the master (microcontrol- ler) and the acknowledgement is issued by the receiving device of the byte (note: the transmitting device must release the sda line (?high?) during the acknowledge pulse.). for example, the slave (mcp3421) issues the acknowledgement (bring down the sda line ?low?) after the end of each receiving byte, and the master (microcontroller) issues the acknowledgement when it reads data from the slave (mcp3421). when the mcp3421 is addressed, it generates an acknowledge after receivi ng each byte successfully. the master device (microcontroller) must provide an extra clock pulse (9th pulse of each byte) for the acknowledgement from the mcp3421 (slave). the mcp3421 (slave) pulls-down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. during reads, the master (microcontroller) can terminate the current read ope ration by not providing an acknowledge bit on the last byte that has been clocked out from the mcp3421. in this case, the mcp3421 releases the sda line to allow the master (microcontroller) to generate a stop or repeated start condition. figure 5-6: data transfer sequence on the serial bus. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition mcp3421 ds22003d-page 18 ? 2007 microchip technology inc. table 5-4: i 2 c serial timing specifications electrical specifications: unless otherwise specified, all limits are specified for t a = -40 to +85c, v dd = +2.7v, +3.3v or +5.0v, v ss = 0v, v in + = v in - = v ref /2. parameters sym min typ max units conditions standard mode clock frequency f scl 0 ? 100 khz clock high time t high 4000 ? ? ns clock low time t low 4700 ? ? ns sda and scl rise time (note 1) t r ? ? 1000 ns from v il to v ih sda and scl fall time (note 1) t f ? ? 300 ns from v ih to v il start condition hold time t hd:sta 4000 ? ? ns after this period, the first clock pulse is generated. repeated start condition setup time t su:sta 4700 ? ? ns only relevant for repeated start condition data hold time (note 3) t hd:dat 0 ? 3450 ns data input setup time t su:dat 250 ? ? ns stop condition setup time t su:sto 4000 ? ? ns stop condition hold time t hd:std 4000 ? ? ns output valid from clock (notes 2 and 3) t aa 0 ? 3750 ns bus free time t buf 4700 ? ? ns time between start and stop conditions. fast mode clock frequency t scl 0 ? 400 khz clock high time t high 600 ? ? ns clock low time t low 1300 ? ? ns sda and scl rise time (note 1) t r 20 + 0.1cb ? 300 ns from v il to v ih sda and scl fall time (note 1) t f 20 + 0.1cb ? 300 ns from v ih to v il start condition hold time t hd:sta 600 ? ? ns after this period, the first clock pulse is generated repeated start condition setup time t su:sta 600 ? ? ns only relevant for repeated start condition data hold time (note 4) t hd:dat 0 ? 900 ns data input setup time t su:dat 100 ? ? ns stop condition setup time t su:sto 600 ? ? ns stop condition hold time t hd:std 600 ? ? ns output valid from clock (notes 2 and 3) t aa 0 ? 1200 ns bus free time t buf 1300 ? ? ns time between start and stop conditions. input filter spike suppression (note 5) t sp 0 ? 50 ns sda and scl pins note 1: this parameter is ensured by characterization and not 100% tested. 2: this specification is not a part of the i 2 c specification. this spec ification is equivalent to the data hold time ( t hd:dat ) plus sda fall (or rise) time: t aa = t hd:dat + t f ( or t r ). 3: if this parameter is too short, it can create an unintended star t or stop condition to other dev ices on the bus line. if this parameter is too long, clock low time (t low ) can be affected. 4: for data input: this parameter must be longer than t sp . if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. for data output: this parameter is charac terized, and tested indirectly by testing t aa parameter. 5: this parameter is ensured by characterization and not 100% tested. this parameter is not available for standard mode. ? 2007 microchip technology inc. ds22003d-page 19 mcp3421 high speed mode clock frequency f scl 0?3.4 1.7 mhz mhz c b = 100 pf c b = 400 pf clock high time t high 60 120 ??ns ns c b = 100 pf c b = 400 pf clock low time t low 160 320 ??nsc b = 100 pf c b = 400 pf scl rise time (note 1) t r ??40 80 ns from v il to v ih ,c b = 100 pf c b = 400 pf scl fall time (note 1) t f ??40 80 ns from v ih to v il ,c b = 100 pf c b = 400 pf sda rise time (note 1) t r: dat ??80 160 ns from v il to v ih ,c b = 100 pf c b = 400 pf sda fall time (note 1) t f: data ??80 160 ns from v ih to v il ,c b = 100 pf c b = 400 pf start condition hold time t hd:sta 160 ? ? ns after this period, the first clock pulse is generated repeated start condition setup time t su:sta 160 ? ? ns only relevant for repeated start condition data hold time (note 4) t hd:dat 0 0 ?70 150 ns c b = 100 pf c b = 400 pf data input setup time t su:dat 10 ? ? ns stop condition setup time t su:sto 160 ? ? ns stop condition hold time t hd:std 160 ? ? ns output valid from clock (notes 2 and 3) t aa ? ? 150 310 ns c b = 100 pf c b = 400 pf bus free time t buf 160 ? ? ns time between start and stop conditions. input filter spike suppression (note 5) t sp 0 ? 10 ns sda and scl pins table 5-4: i 2 c serial timing specifications (continued) electrical specifications: unless otherwise specified, all limits are specified for t a = -40 to +85c, v dd = +2.7v, +3.3v or +5.0v, v ss = 0v, v in + = v in - = v ref /2. parameters sym min typ max units conditions note 1: this parameter is ensured by characterization and not 100% tested. 2: this specification is not a part of the i 2 c specification. this spec ification is equivalent to the data hold time ( t hd:dat ) plus sda fall (or rise) time: t aa = t hd:dat + t f ( or t r ). 3: if this parameter is too short, it can create an unintended star t or stop condition to other dev ices on the bus line. if this parameter is too long, clock low time (t low ) can be affected. 4: for data input: this parameter must be longer than t sp . if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. for data output: this parameter is charac terized, and tested indirectly by testing t aa parameter. 5: this parameter is ensured by characterization and not 100% tested. this parameter is not available for standard mode. mcp3421 ds22003d-page 20 ? 2007 microchip technology inc. figure 5-7: i 2 c bus timing data. t f scl sda t su:sta t sp t hd:sta t low t high t hd:dat t aa t su:dat t r t su:sto t buf ? 2007 microchip technology inc. ds22003d-page 21 mcp3421 6.0 basic application configuration the mcp3421 device can be used for various precision analog-to-digital converter applications. the device operates with very simp le connections to the application circuit. the following sections discuss the examples of the device connections and applications. 6.1 connecting to the application circuits 6.1.1 input voltage range the fully differential input signals can be connected to the v in + and v in - input pins. the input range should be within absolute common mode input voltage range: v ss - 0.3v to v dd + 0.3v. outside this limit, the esd protection diode at the input pin begins to conduct and the error due to input leakage current increases rapidly. within this limit, the differential input v in (= v in +-v in -) is boosted by the pga before a conversion takes place. the mcp3421 can not accept negative input voltages on the input pins. figure 6-1 and figure 6-2 show typical connection examples for differential inputs and a single-ended input, respectively. for the single-ended input, the input signal is applied to one of the input pins (typically connected to the v in + pin) while the other input pin (typically v in - pin) is grounded. the input signal range of the single- ended configuration is from 0v to 2.048v. all device characteristics hold for the single-ended configuration, but this configuration loses one bit resolution because the input can only stand in positive half scale. refer to section 1.0 ?electrical characteristics? . 6.1.2 bypass capacitors on v dd pin for accurate measurement, the application circuit needs a clean supply voltage and must block any noise signal to the mcp3421 device. figure 6-1 shows an example of using two bypass capacitors (a 10 f tantalum capacitor and a 0.1 f ceramic capacitor) in parallel on the v dd line. these capacitors are helpful to filter out any high frequency noises on the v dd line and also provide the momentary bursts of extra currents when the device needs from the supply. these capacitors should be placed as close to the v dd pin as possible (within one inch). if the application circuit has separate digital and analog power supplies, the v dd and v ss of the mcp3421 should reside on the analog plane. 6.1.3 connecting to i 2 c bus using pull-up resistors the scl and sda pins of the mcp3421 are open-drain configurations. these pins r equire a pull-up resistor as shown in figure 6-1 . the value of these pull-up resistors depends on the operating speed (standard, fast, and high speed) and loading capacitance of the i 2 c bus line. higher value of pull-up resistor consumes less power, but increases the signal transition time (higher rc time constant) on the bus. therefore, it can limit the bus operating speed. the lower value of resistor, on the other hand , consumes higher power, but allows higher operating speed. if the bus line has higher capacitance due to long bus line or high number of devices connected to the bus, a smaller pull-up resistor is needed to compensate the long rc time constant. the pull-up resistor is typically chosen between 1 k and 10 k ranges for standard and fast modes, and less than 1 k for high speed mode in high loading capacitance environments. figure 6-1: typical connection example for differential inputs. figure 6-2: typical connection example for single-ended input. the number of devices connected to the bus is limited only by the maximum bus capacitance of 400 pf. the bus loading capacitance affects on the bus operating speed. for example, the highest bus operating speed for the 400 pf bus capacitance is 1.7 mhz, and 3.4 mhz for 100 pf. figure 6-3 shows an example of multiple device connections. mcp3421 v in + v in - v dd v ss 1 2 3 4 5 6 scl sdl 10 f 0.1 f r r input signals v dd v dd t o mcu (master) note: r is the pull-up resistor. mcp3421 v in + v in - v dd v ss 1 2 3 4 5 6 scl sdl 10 f 0.1 f r r input signals v dd v dd t o mcu (master) note: r is the pull-up resistor. mcp3421 ds22003d-page 22 ? 2007 microchip technology inc. figure 6-3: example of multiple device connection on i 2 c bus. 6.2 device connection test the user can test the pres ence of the mcp3421 on the i 2 c bus line without performing an input data conver- sion. this test can be achieved by checking an acknowledge response from the mcp3421 after send- ing a read or write command. here is an example using figure 6-4 : (a) set the r/w bit ?high? in the address byte. (b) the mcp3421 will then acknowledge by pulling sda bus low during the ack clock and then release the bus back to the i 2 c master. (c) a stop or repeated start bit can then be issued from the master and i 2 c communication can continue. figure 6-4: i 2 c bus connection test. 6.3 application examples the mcp3421 device can be used in a broad range of sensor and data acquisition applications. figure 6-5 , shows an example of interfacing with a bridge sensor for pressure measurement. figure 6-5: example of pressure measurement. in this circuit example, the sensor full scale range is 7.5 mv with a common mode input voltage of v dd / 2. this configuration will provide a full 14-bit resolution across the sensor output ran ge. the alternative circuit for this amount of accuracy would involve an analog gain stage prior to a 16-bit adc. figure 6-6 shows an example of temperature measure- ment using a thermistor. th is example can achieve a linear response over a 50 c temperature range. this can be implemented using a standard resistor with 1% tolerance in series with the thermistor. the value of the resistor is selected to be e qual to the thermistor value at the mid-point of the desired temperature range. figure 6-6: example of temperature measurement. sda scl (24lc01) microcontroller eeprom mcp3421 (tc74) temperature sensor (pic16f876) 123456789 scl sda 1 1 0 1a2a1a0 1 start bit address byte address bits device bits r/w start bit mcp3421 ack response npp301 mcp3421 v in + v in - v dd v ss 1 2 3 4 5 6 scl sdl 10 f 0.1 f r r v dd v dd t o mcu (master) v dd 10 k resistor 10 k thermistor mcp3421 v in + v in - v dd v ss 1 2 3 4 5 6 scl sdl 10 f 0.1 f r r v dd v dd t o mcu (master) v dd ? 2007 microchip technology inc. ds22003d-page 23 mcp3421 7.0 packaging information 7.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 1 6-lead sot-23 xxnn example 1 ca25 part number address option code mcp3421a0t-e/ch a0 (000) cann mcp3421a1t-e/ch a1 (001) cbnn mcp3421a2t-e/ch a2 (010) ccnn mcp3421a3t-e/ch a3 (011) cdnn mcp3421a4t-e/ch a4 (100) cenn mcp3421a5t-e/ch a5 (101) cfnn mcp3421a6t-e/ch a6 (110) cgnn mcp3421a7t-e/ch a7 (111) chnn mcp3421 ds22003d-page 24 ? 2007 microchip technology inc. ! " #$ " % & ' ( ( ) * ( + , * $--((( - * . /00/%1 0 /2 23 4 25 , 2 6 , 7! " # 3 0 , 7 " # 3' 8 7 9 ! , * %* :7 9 ; 9 ! 3' < 9 ; , * < ; 9 : 3' 0 9 ; ) 0 0 9 6 ) 0 ;! 9 : ) = 9 ;= 0 %* : 9 6 0 < 5 9 ! b e 4 n e1 pin1idby laser mark d 1 2 3 e e1 a a1 a2 c l l1 % & ( # >:" ? 2007 microchip technology inc. ds22003d-page 25 mcp3421 appendix a: revision history revision d (november 2007) the following is the list of modifications: 1. section 1.0 electrical characteristics: changed gain error drift typical from 5 to 15, and maxi- mum from 40 to ?. revision c (october 2007) the following is the list of modifications: 1. figure 5-4: changed o/c designation to o /c. 2. updated package outline drawing. 3. updated revision history. revision b (december 2006) the following is the list of modifications: 1. changes to electrical characteristics tables 2. added characterization data 3. changes to i 2 c serial timing specification table 4. change to figure 5-7. 5. updated package outline drawings revision a (august 2006) ? original release of this document. mcp3421 ds22003d-page 26 ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. ds22003d-page 27 mcp3421 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp3421: single channel ? a/d converter address options: xx a2 a1 a0 a0 *=000 a1=001 a2=010 a3=011 a4=100 a5=101 a6=110 a7=111 * default option. contact microchip factory for other address options tape and reel: t = tape and reel temperature range: e = -40c to +125c package: ch = plastic small outline transistor (sot-23-6), 6-lead examples: a) mcp3421a0t-e/ch: tape and reel, single channel ? a/d converter, sot-23-6 package, address option = a0. part no. x xx address temperature range device /xx package options x tape and reel mcp3421 ds22003d-page 28 ? 2007 microchip technology inc. notes: ? 2007 microchip technology inc. ds22003d-page 29 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip te chnology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds22003d-page 30 ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 10/05/07 |
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